ID:186320 DDR pin group must have registers feeding DQ I/O pins driven by DQS I/O pin "<name>" that are clocked by same PLL output signal

CAUSE: Double data rate (DDR) pin group has registers feeding the DQ I/O pins driven by the specified DQS I/O pin that are not driven by the same PLL output signal as the clock, but the registers must be clocked by the same PLL output signal.

ACTION: Modify the design so that the same PLL output signal is used as the clock of the registers feeding the DQ I/O pins.