List of Messages |
CAUSE: Double data rate (DDR) pin group has an output of the specified DQ I/O pin to the device that feeds the datain port of fewer than two registers, but the output of the DQ I/O pin must feed the datain port of at least two registers
ACTION: Modify the design so the output of the DQ I/O pin to the device feeds the datain port of at least two registers.
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