List of Messages
Parent topic: List of Messages

ID:186052 Input clock frequency of fast PLL "<name>" that drives dedicated SERDES receivers with dynamic phase alignment mode is <number> MHz, but the minimum allowed is <number> MHz

CAUSE: The input clock frequency you set on the specified fast PLL is lower than the minimum allowed on the device.

ACTION: Modify the PLL so that the input clock frequency is higher than the minimum required.

Parent topic: List of Messages

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