List of Messages |
CAUSE: The registers feeding the DQ or DQS I/O pin are not driven by the same PLL output signal as the clock, but the registers must be clocked by the same PLL output signal.
ACTION: Modify the design so that the same PLL output signal is used as the clock of the registers feeding the specified DQ or DQS I/O pin.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.