ID:186407 DDR pin group must have at least two registers that generate signal that feeds output enable port of DQS or DQ I/O pin "<name>"

CAUSE: Double data rate (DDR) pin group has fewer than two registers generating the output enable signal for the specified DQS I/O or DQ I/O pin, but it must have at least two registers to generate the output enable signal.

ACTION: Modify the design to use at least two registers to generate the output enable signal for the DQS or DQ I/O pin.