ID:186042 Fast PLL <name> has input clock <name> with I/O standard <name> and this PLL drives differential I/O pins having I/O standard <name> - clock and data IO standards should be the same. This might happen if the input clock is driving two or more PLL's with different I/O standard on their differential I/O pins

CAUSE: The specified input clock pin drives more than one fast PLL. You assigned different differential I/O standards to the input clock and the differential I/O pins of at least one of the fast PLLs.

ACTION: Modify the design so that the input clock and all differential I/O pins of all the fast PLLs driven by this input clock have the same differential I/O standard.