List of Messages |
CAUSE: The design has the specified number of nodes that need to be fed by a clock pin or the output of a phase-locked loop (PLL), but only the specified number of locations of clock pins or PLL outputs are available. Click the + icon to display information on the locations of clock pins or PLL outputs that are available to feed a node.
ACTION: Modify the design so that some of the nodes can use a different location, or reduce the number of nodes that need to be fed by clock pins or PLL outputs.
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