List of Messages |
CAUSE: Design contains one or more memory blocks that use a global signal on the clock-enable1 port of the RAM and there is not legal routing support for this configuration.
ACTION: Change the signal source of the clock-enable1 port to use no control signal or a non-global control signal.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.