List of Messages
Parent topic: List of Messages

ID:176715 Fast PLL <name> drives TX channels with <number> MHz for output clock frequency, but the target device or companion device <name> can support only <number> MHz maximum output clock frequency for TX channels.

CAUSE: You have set the TX output clock frequency beyond the specified legal limit for the device.

ACTION: You must set the TX output clock frequency correctly depending on the device or device migration compiled.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.