List of Messages |
CAUSE: The specified input clock pin of the netlist drives more non-DPA RX fast PLL than is possible on the device in compensated-mode. To be a non-DPA RX PLL, the fast PLL drives at least one non-DPA-mode SERDES. As a result, the input clock pin must be placed in a compensated I/O location. There does not exist a location on the device for the input clock pin.
ACTION: Modify the design so that each input clock pin drives no more than the maximum number of non-DPA RX PLLs or change the driven SERDES to be in DPA-mode.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.