List of Messages |
CAUSE: The previous post-compilation netlist for the design contains an illegal connection from the specified node. As a result, the Fitter cannot perform a incremental SignalProbe compilation, SignalTap II incremental routing connection or ECO fitting. This message can occur when the netlist has been manually edited to produce an illegal connection, either in the Chip Planner or directly in the Verilog Quartus Mapping File (.vqm) for the project.
ACTION: If you created this connection using the Chip Planner or manually edited the VQM File for the project, remove or change the connection. For further assistance contact Altera Technical Support by creating a Service Request at www.altera.com/mysupport or the EDA tool vendor support for more information.
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