CAUSE: You created a
LogicLock region and assigned the specified cells to the region. However, the Fitter is unable to satisfy this constraint. On or more of the reasons are:
- The assignments require more entities in this region than the device can contain.
- If the entities are LABs, the Fitter was unable to divide the related logic cells into a small enough number of LABs so that they will all fit in the specified region.
- There are carry and cascade chains, and limitations on the number of clock enables, clocks, asynchronous clears and so on per LAB. The Fitter is unable to divide all the logic cells assigned to a region into a small enough number of legal LABs to fit in that region.
- If the entities are RAM cells, the Fitter is unable to divide them into a small enough number of memory block locations so that they will all fit in the specified region. Different address and control lines or different modes may prevent two RAM cells from sharing the same memory block.
- There are LogicLock regions in the design. The design elements assigned to one or more of these regions require more resource blocks than the regions contain.
- Resource blocks of the specified type that are in the region are also covered by a LogicLock region with the Reserved property set to On or Limited. The Fitter cannot use these resource blocks to fit design elements that are not members of the reserved LogicLock region.