List of Messages
Parent topic: List of Messages

ID:167101 Unable to place PLL "<name>" at location "<name>" because the PLL's input clock pin is not assigned a supported transceiver pin I/O standard

CAUSE: The Quartus Prime software is unable to place the specified Phase-Locked Loop (PLL) due to problems related to the PLL's input clock pin I/O standard.

ACTION: Change either the I/O standard or the location assignments for the specified PLL.

Parent topic: List of Messages

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