ID:167090 Transceiver channels clocked by clock divider atom "<name>" are configured at a data rate that is higher than that supported by nominal power supply levels in Stratix IV GX devices. Elevated voltage supply levels are required in Stratix IV GX devices in this configuration. For more technical details and elevated power supply requirements, refer to the Stratix IV GX Errata Sheet sections "Higher Transceiver Power Supply Levels for -2 Speed Grade" and "x8 and xN Clock Line Timing Issue for Transceivers". Contact Altera Technical Support on mySupport for a work around for successful compilation.

CAUSE: Transceiver channels clocked by clock divider atom \"%1!s!\" are configured at a data rate that is higher than that supported by nominal power supply levels in Stratix IV GX devices. Elevated voltage supply levels are required in Stratix IV GX devices in this configuration. For more technical details and elevated power supply requirements, refer to the Stratix IV device Errata Sheet sections \"Higher Transceiver Power Supply Levels for -2 Speed Grade\" and \"x8 and xN Clock Line Timing Issue for Transceivers\".

ACTION: Contact Altera Technical Support on mySupport for a work around for successful compilation.