List of Messages
Parent topic: List of Messages

ID:167089 Transceiver channels clocked by clock divider atom "<name>" are configured at a data rate that is higher than that supported in Stratix IV GX/GT devices. The data rate limitation is due to a xN clock line issue. For more details on the impact of xN clock line issue, refer to the Stratix IV GX or Stratix IV GT Errata sheet section "x8 and xN Clock Line Timing Issue for Transceivers".

CAUSE: Transceiver channels in Stratix IV GX/GT devices may transmit incorrect serial bits due to skew accumulated on the xN clock lines. For more details on the impact of xN clock line issue, refer to the Stratix IV GX or Stratix IV GT errata section \"x8 and xN Clock Line Timing Issue for Transceivers\".

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Parent topic: List of Messages

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