List of Messages
Parent topic: List of Messages

ID:16669 Your design contains an I/O clock divider node, which requires that the design also contain the DQ group logic option assignment. Turn on the DQ Group logic option in the Assignment Editor, or if your design uses a memory interface with UniPHY IP core, run the <variation name>_pin_assignments.tcl file.

CAUSE: Your design contains an I/O clock divider node, but does not contain the required DQ group logic option assignment.

ACTION: Turn on the DQ Group logic option in the Assignment Editor, or if your design uses a memory interface with UniPHY IP core, run the <variation name>_pin_assignments.tcl file.

Parent topic: List of Messages

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