| List of Messages | |
CAUSE: The DQS I/O pin is constrained to a pin that does not support its dual-purpose clock pin delay setting.
ACTION: Modify the design so that the pin has a different location constraint, or remove the dual-purpose clock pin delay setting from the pin.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.