List of Messages |
CAUSE: Your design contains a memory interface configuration that might not function correctly in the selected Stratix V Engineering Sample (ES) device with the current I/O pin placement.
ACTION: All Stratix V production devices function correctly with the current pin placement. If you did not implement your design with ES devices, change the targeted device to a non-ES part. You can avoid this problem by constraining some I/Os to different locations in the FPGA. For a list of impacted I/Os, consult the sub-messages. For further assistance on how to resolve this issue, contact Altera technical support directly.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.