List of Messages |
CAUSE: You restricted the specified counter to be used for the specified clock output of the specified PLL with the Preserve PLL Counter Order logic option (that is, the PRESERVE_PLL_COUNTER_ORDER option is turned on in the Quartus Prime Settings File (.qsf)). In order to implement the requested multiply and divide ratios for the clock output port, cascaded counters must be used. However, the cascaded counters cannot be implemented because no other counter cascades into the specified counter.
ACTION: Use a counter that can have a cascade input port, modify the multiply and divide ratios so that cascaded counters are not needed, or modify the counters so they are not restricted to be used for the clock outputs and allow the Compiler to choose the counters automatically instead.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.