List of Messages |
CAUSE: The specified phasectrlin input of the specified I/O clock divider block is not driven by the specified resyncinputphasesetting output of a DQS configuration primitive while the USE_PHASECTRLIN parameter is set to TRUE.
ACTION: Check the design and make sure that the specified phasectrlin input of the specified I/O clock divider block is driven by the specified resyncinputphasesetting output of a DQS configuration primitive. Alternatively you can set the USE_PHASECTRLIN parameter to a value other than TRUE.
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