List of Messages |
CAUSE: The USE_PHASECTRLIN and PHASE_SETTING parameters of the specified I/O clock divider primitive are not set to FALSE and 0 respectively while the clk input is driven by the dqsbusout output of a DQS delay chain primitive.
ACTION: Set the USE_PHASECTRLIN and PHASE_SETTING parameters of the specified I/O clock divider primitive to FALSE and 0 respectively. Alternatively, you can change your design so that the clk input of the specified I/O clock divider primitive is not driven by the dqsbusout output of a DQS delay chain primitive.
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