List of Messages |
CAUSE: For the specified WYSIWYG RAM primitive, signal ENA0 or ENA1 is connected, but port clk0 or clk1 is not connected, however, the clock port must be connected when signal ENA0 or ENA1 is connected.
ACTION: Connect the specified clock port.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.