List of Messages |
CAUSE: The Quartus Prime software cannot find the legal settings for the specified PLL with the specified reference clock frequency and output clock frequency with ES silicon.
ACTION: Specify a legal set of reference clock frequency and output clock frequency such that the 14G VCO is not required to be engaged.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.