List of Messages |
CAUSE: The pllcalibrateclk and plldataclk input ports of the specified Clock Delay Control Calibration blocks are fed by the clock output ports of the two specified PLLs. The pllcalibrateclk and plldataclk input ports of a Clock Delay Control Calibration block must always be fed by the clock output ports of the same PLL.
ACTION: Modify the design so that the clock output ports of the same PLL feeds the pllcalibrateclk and plldataclk input ports of the specified Clock Delay Control Calibration block.
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