List of Messages |
CAUSE: The specified SERDES receiver or transmitter atom has enable0 and clock0 input ports that can be driven only by a valid indexed enable and sclk output ports of a fast PLL. The LVDS SERDES enable0 being driven by PLL enable0 must also have an LVDS SERDES clock0 driven by PLL sclk0, and the LVDS SERDES enable0 being driven by PLL enable1 must also have an LVDS SERDES clock0 driven by PLL sclk1. This error usually occurs when you instantiate a megafunction directly in a text file rather than using the MegaWizard Plug-In Manager .
ACTION: Modify the design so that the enable0 and a clock input ports of the SERDES receiver atom have valid sources.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.