List of Messages |
CAUSE: The input reference clock of the specified fractional PLL is not driven by a dedicated clock pin. As a result, the PLL would have inadequate jitter performance. The Fitter requires input reference clocks to be placed on clock pins.
ACTION: Assign the clock for the PLL to a dedicated clock pin.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.