List of Messages |
CAUSE: The Fitter encountered congestion in this section clock (SCLK) network while trying to connect the clock driver to its fan-outs. Clock routing from global sources has limited routing to elements in this spine region and your design may try to exceed that limit.
ACTION: Use the Chip Planner to view the congested region and driving cells. Remove clock driver location constraints, if needed, to allow the Fitter to try different locations in different regions. You may also attempt to reduce the clock network usage in your design, either by using fewer clocks, or by using smaller clocks instead of larger clocks. For example, you can use regional clocks instead of global clocks where possible.
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