List of Messages |
CAUSE: Your design routes the specified signal to the specified network, however the signal requires the use of regular core routing and there is not a path to reach the specified clock network from internal logic.
ACTION: To drive the specified clock type, refer to the Core Fabric and General Purpose I/Os Handbook for the target device family for legal source types, and modify the design to use a clock source of a compatible type; for example, clock input pin or PLL output. If the clock signal must originate from internal logic, modify the assignments on the signal to use a different global clock type, or you can choose to not route this signal on a dedicated clock network.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.