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CAUSE: The Quartus Prime Netlist Optimizations from a previous compilation moved I/O cells into this partition because of timing assignments, or Fast Input Register or Fast Output Register assignments. These optimizations were preserved in the current compilation because you directed Partition Merge to use the Post-Fir Netlist Type for this partition. You also made changes to the connected partitions to introduce new logic or connections between the top-level pin and the partition port. Because the partition port contains an I/O cell, the additional logic or connections cannot be legally implemented, causing this error. As a rule, an I/O cell can only have a single, wire connection to a pin.
ACTION: If you intend to keep the changes made to the connected partitions, you must recompile the specified partition using a Post-Synthesis, an Imported, or a Source File netlist, so that the I/O cells can be removed. Otherwise, update the HDL to remove the illegal logic or connections. To understand the types of Netlist Optimizations that can cause this error, Altera recommends that you consult the Quartus Prime Handbook chapter on incremental compilation.
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