| List of Messages | |
CAUSE: The specified net is connected to a signal or variable declared in VHDL or System Verilog packages but does not have a source or is connected directly to VCC or GND.
ACTION: You must connect the specified net to the output of a logic function.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.