Remove Redundant Logic Cells logic option

A logic option that removes redundant LCELL primitives or WYSIWYG primitives. Turning on this option optimizes a circuit for area and speed.

This option is a project-wide option. This option is available for all Altera devices supported by the Quartus® Prime Standard Edition software except MAX3000 and MAX7000 devices.

Scripting Information

Keyword: remove_redundant_logic_cells

Settings: on | off

*default

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