A logic option that forces the compiler to utilize synchronous clear signals in normal mode logic cells. Turning this option on helps to reduce the total number of logic cells used in the design, but may negatively impact the fitting since synchronous control signals are shared by all logic cells in a Logic Array Block (LAB) Definition
This option is available for all Altera devices supported by the Quartus® Prime Standard Edition software except MAX3000 and MAX7000 devices.
Scripting Information |
Keyword:force_synch_clear Settings:on | off *default |