A logic option that forces the fan-out of the slave Phase-Locked Loop (PLL) Definition clock output to be merged into the master PLL clock output. This option should be used only for static PLL clock outputs.
This option is available for supported device(Arriaseries, CycloneIII, CycloneIV, StratixIII, and StratixIV) families.
Scripting Information |
Keyword:force_merge_pll_fanouts Settings:on | off |