Auto Merge PLLs logic option

A logic option that allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs used in a design.

This option is useful for decreasing the total number of PLLs in a design that did not fit into the target device during compilation. Also, by assigning this option to node-specific bases, you can prevent specific PLLs from merging. When the COMMON_RX_TX_PLL parameter is turned ON, the altlvds_tx and altlvds_rx megafunctions automatically use this option.

This option is ignored if it is applied to anything other than a node. This option is available for all Altera devices supported by the Quartus® Prime Standard Edition software except ArriaVGZ, MAXII, MAX V, MAX3000, MAX7000, and StratixV devices.

Scripting Information

Keyword: auto_merge_plls

Settings:on | off

*default

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