A logic option that allows you to specify the retiming behavior for a sequence of synchronization or metastability registers. All registers in the sequence have the same clock and have no fan-out in between, such that the first register is fed by a pin or by logic in another clock domain. These registers are not moved during gate-level retiming. The length of the sequence is specified by a variable.
This option is available for all Altera devices supported by the Quartus® Prime Standard Edition software except MAX3000 and MAX7000 devices.
Scripting Information |
Keyword: synchronization_register_chain_length Settings:2 | <register value> *default |