Parent topic: Quartus Prime Standard Edition Verilog HDL Support Parent topic: Quartus Prime Standard Edition Verilog HDL Support

Section 4—Expressions

Section

Construct

Quartus® Prime Standard Edition Support

4.1

Operators

Supported as defined below.

4.1.5

Arithmetic Operators

Supported

4.1.7

Relational Operators

Supported

4.1.8

Equality Operators

Supported

4.1.9

Logical Operators

Supported

4.1.10

Bit-Wise Operators

Supported

4.1.11

Reduction Operators

Supported

4.1.12

Shift Operators

Supported

4.1.13

Conditional Operators

Supported

4.1.14

Concatenations

Supported

4.1.15

Event or Operators

Supported

4.2

Operands

Supported as defined below.

4.2.1

Bit-Select and Part-Select Operands

Supported

4.2.2

Memory Addressing

Supported

4.2.3

String Operands

Supported

4.3

Minimum, Typical, and Maximum Delay Expressions

Supported. Ignored for synthesis.
Parent topic: Quartus Prime Standard Edition Verilog HDL Support Parent topic: Quartus Prime Standard Edition Verilog HDL Support

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