Organizing a VHDL Design into Libraries

A VHDL library stores analyzed design units. Every design unit in a VHDL design must be compiled into a library, and two design units with the same name cannot be compiled into the same library. For example, if a design contains declares two packages with the same name, it must compile the packages into different libraries. By default, the Quartus^® Prime software compiles all VHDL files into the work library. If a VHDL design refers to a library that does not exist, or if the library does not contain a referenced design unit, the software searches for the design unit in the work library. This behavior allows the Quartus II software to compile most VHDL designs with minimal setup.

Prior to analyzing the sources files in a design, you may specify a different destination library for the design units in a source file. You can use one of the following three methods, described in more detail below:

In the File Properties dialog box in the Quartus^® Prime graphical user interface (GUI)
In the Quartus Settings File (.qsf) or with a Tcl command
In the VHDL file itself, using a synthesis directive

When the Quartus^® Prime Compiler analyzes the file (in a flow that requires analysis of the source file), it stores the analyzed design units in the file's destination library.

Note: Specifying the library name through the GUI, QSF or Tcl allows you to specify only a single destination library for all the design units in a given source file. This synthesis directive allows you to change the destination VHDL library within a source file, providing the option of organizing the design units in a single file into different libraries, rather than just a single library.

The Quartus^® Prime software gives an error if you use the library directive in the middle of a design unit.