A VHDL synthesis attribute that assigns device pins to a port on a VHDL entity.
To use the chip_pin synthesis attribute in a VHDL Design File (.vhd) Definition, declare the synthesis attribute using an Attribute Declaration, and then set the value of the chip_pin synthesis attribute on an entity port using an Attribute Specification that you place in the entity's underlying architecture. The value of the chip_pin synthesis attribute must be a string literal containing a list of device pin names separated by commas (,).
You can use the chip_pin synthesis attribute only on entity ports with single-bit or one-dimensional types. For one-dimensional ports, the port's range declaration determines the mapping of pins listed in the synthesis attribute to individual bits in the port. For example, in the following code, the chip_pin synthesis attribute assigns device pins to ports sel and data on entity foo:
entity foo is port (sel : in std_logic; data : in std_logic_vector(3 downto 0); o : out std_logic); end foo; architecture rtl of foo is attribute chip_pin : string; attribute chip_pin of sel : signal is "C4"; attribute chip_pin of data : signal is "D1, D2, D3, D4"; begin -- Specify additional code end architecture;
In this example, sel is a one bit wide port; pin C4 is assigned to this port. data is a one-dimensional port that is four bits wide. Because data is declared with type std_logic_vector(3 downto 0), pin D1 is assigned to data(3), pin D2 is assigned to data(2), and so forth. If you declared data with type std_logic_vector(0 to 3), pin D1 would be assigned to data(0), pin D2 would assigned to data(1), and so forth.
You cannot use the chip_pin synthesis attribute to make pin assignments on non-entity ports or ports with more than two dimensions.