OR Primitive

Names:

OR2,OR3,OR4,OR6,OR8,OR12

Output Description:

OUT = logical OR of inputs

Input Description:

IN1, IN2, ...IN12= 2, 3, 4, 6, 8, or 12 inputs
Note: In Verilog HDL, you must use the built-in or gate primitive to implement the OR logic function. Go to Using a Verilog HDL Gate Primitive for more information.

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