Subdesign Section (AHDL)

The Subdesign Section declares the input, output, and bidirectional ports of the Text Design File (.tdf).

The following example shows a Subdesign Section:

SUBDESIGN top
(
        foo, bar, clk1, clk2    : INPUT = VCC;
        a0, a1, a2, a3, a4      : OUTPUT;
        b[7..0]                                 : BIDIR; 
)

The Subdesign Section has the following characteristics:

• The keyword SUBDESIGN is followed by the subdesign name. The subdesign name must be the same as the TDF file name. In the example shown above, the subdesign name is top.
• The list of signals is enclosed in parentheses ().
• Signal names are represented by symbolic names such as foo, and are assigned a port type such as INPUT.
• Signal names are separated by commas (,), are followed by a colon (:) and a port type, and end with a semicolon (;).
• The port type may be INPUT, OUTPUT, or BIDIR. In the example shown above, the foo, bar, clk1, and clk2 signals are inputs and a0, a1, a2, a3, and a4 are outputs. The bus b[7..0] is bidirectional.
• You can optionally assign a default value of GND or VCC after the port type (otherwise, no default value is assumed). In the example shown above, VCC is the default value for the input signals unless they are assigned in a higher-level file (assignments in a higher-level file take precedence).

In a top-level design file, INPUT, OUTPUT, and BIDIR port types represent actual device pins. In a lower-level design file, all port types are the inputs and outputs of the file, but not of the project itself.