Creating a Design for Use with the Precision RTL Synthesis Software

You can create VHDL and Verilog HDL design files with the Quartus^® Prime Standard Edition Text Editor or another standard text editor for use with the Mentor Graphics Precision RTL Synthesis software.

To create a VerilogHDL or VHDL design file for use with the Precision RTL Synthesis software:

If you have not already done so, set up the Precision RTL Synthesis working environment.
Enter a VHDL or Verilog HDL design in the Quartus^® Prime Standard Edition Text Editor or another standard text editor and save it in your working directory.
To use megafunctions in a design, use the IP Catalog to generate and instantiate a megafunction variation. You can use the IP Catalog to create LVDS or RAM Definition functions. Refer to the Creating and Instantiating Altera-Provided Functions in Other EDA Tools topic for examples on how to use Altera-provided megafunctions and library of parameterized modules (LPM) functions in other EDA design entry/synthesis tools.
In addition, the Precision RTL Synthesis software automatically recognizes certain types of HDL code and maps them to Altera megafunctions during synthesis. You can describe the design in VerilogHDL or VHDL and use the Precision RTL Synthesis software to infer multipliers, multiply-accumulators, multiply-adders, RAM, and ROM functions directly from HDL code.
To continue with the Precision RTL Synthesis design flow, proceed to set up a project with the Precision RTL Synthesis software.