To compile libraries and design files with command-line commands

If you have not already done so,set up a QuestaSim project with command lines.
Important: If your design contains the alt2gxb megafunction, refer to the appropriate megafunction topic for required settings.

Enter the following commands to direct the QuestaSim software to compile the appropriate libraries and design files for VHDL designs.

If your design contains the alt2gxb megafunction, type the following commands at the QuestaSim prompt:

vlib lpm    
vlib altera    
vlib sgate    
vmap lpm work    
vmap altera work    
vmap sgate work    
vcom -worklpm<path to library>/  220pack.vhd  
vcom-work lpm <path to library>/220model.vhd    
vcom -work sgate  <path to library>/  sgate_pack.vhd  
vcom -work sgate<path to library>/sgate.vhd  
vcom -work stratixiigx_gxb<path to library>/stratixiigx_hssi_atoms.vhd.vhd  
vcom -work stratixiigx_gxb<path to library>/stratixiigx_hssi_components.vhd

or, for a design targeting a StratixIV GX device:

vcom -work stratixivgx_gxb <path to library>/stratixivgx_hssi_atoms.vhd.vhd    
vcom -work stratixivgx_gxb <path to library>/stratixivgx_hssi_components.vhd

To compile the device-specific simulation models, VHDL Output File, and test bench file (if you are using one), type the following commands at the QuestaSim prompt:

vcom -work work <path to library>/<device family> _components.vhd  
vcom -work work <path to library>/<device family>_atoms.vhd  
vcom -work work <design name>.vho  
vcom -work work <test bench>.vhd

Enter the following commands to direct the QuestaSim software to compile the appropriate libraries and design files for Verilog HDL designs.
To compile the device-specific simulation models, Verilog Output File, and test bench file (if you use one), type the following commands at the QuestaSim prompt:
```
vlog -work work   <path to library>/<device family> _atoms.v  
vlog -work work <design name>.vo  
vlog -work work <test bench>.v
```