Design Entry/Synthesis Page (Settings Dialog Box) |
Displays a list of available input synthesis formats for your selected EDA input tool. Depending on which synthesis formats your tool supports, available formats can include Verilog HDL, VHDL, AHDL, EDIF Input File (.edf) Definition, or Verilog Quartus Mapping File (.vqm) Definition
Scripting Information |
Keyword:eda_input_data_format Settings:"VQM" | "Verilog HDL" | "VHDL" | "EDIF" | AHDL |