Directs the EDA Netlist Writer to maintain the original user design hierarchy when generating the VHDL Output File (.vho) Definition or Verilog Output File (.vo) Definition output netlist for the project.
Allows you to maintain the hierarchy in gate-level simulation netlists for debugging purposes. You can use this option during debugging to aid in identifying the location of a particular node within an entity.
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Information |
Keyword:eda_maintain_design_hierarchy Settings:on | off *default |