The Quartus® Prime Pin Planner helps you visualize, plan, and assign device I/O pins in a graphical view of the target device package. You can quickly locate various I/O pins and assign them design elements or other properties to ensure compatibility with your PCB layout. The Quartus® Prime software uses the assignments to place and route your design during device programming. The Pin Planner can also help with early pin planning by allowing you to plan for and assign nodes not yet defined in the design. The Pin Planner Task window provides one-click access to common pin planning tasks. After clicking a pin planning task, you view and highlight the results in the Report window by selecting or deselecting I/O types.
You can use the Pin Planner to quickly locate specific pin types, such as I/O banks, VREF groups, edges, DQ/DQS pins, hard memory interface pins, PCIe hard IP interface pins, hard processor system pins, and clock region input pins. You can then assign design elements, I/O standards, IP cores, and other properties to the device I/O pins by name or by drag and drop. Once you define and assign the logic or options, you can generate a top-level design file to include in the project.You can filter and search the nodes in the design, as well as define custom node groups for assignment.The Pin Planner allows you to access Board Trace Model assignments for Advanced I/O Timing and to view pin migration compatibility. You can use the live I/O check feature to verify the legality of pin assignments against VCCIO, VREF, electromigration (current density), Simultaneous Switching Output (SSO), drive strength, I/O standard, PCI_IO clamp diode, and I/O pin direction compatibility rules.