Gated Clock Should be Implemented According to Altera Standard Scheme (Design Assistant Rule)

 


In a design, you can use combinational logic as a clock signal that can prevent certain logic in a circuit from being activated by the clock signal and can therefore reduce the total power consumption of a device. The combinational logic that is used as a clock signal should follow the following guidelines:

The following image shows an example of combinational logic used as a clock signal, where the gating logic is a two-input AND gate:

 

The following image shows an example of combinational logic used as a clock signal, where the gating logic is a two-input OR gate:


Important: This rule can be turned on or off as a global setting for the entire design on the Design Assistant page; or enabled or disabled for nodes, entities, or instances with Rule C101. This rule has a Critical severity level.

 

 

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