Allows you to select Synopsys Design Constraints Files to include in the project, and view the list of included files. You can also arrange the files in the order that you want the TimeQuest analyzer to read them. To prevent compilation errors, you must reorder files if they have dependencies. For example, if Synopsys Design Constraints File A depends on constraints in Synopsys Design Constraints File B, then you must list file B before file A.

Where a Synopsys Design Constraints File is included in a Quartus II Project File (.qpf), the Quartus II IP File is included in this list as well.

Directs the TimeQuest analyzer to use Advanced I/O Timing to compute delays from the I/O buffer to the pin for each output and bidirectional pin. The TimeQuest analyzer computes these delays with the board trace model specified in the Board Trace Model tab of the Device and Pin Options dialog box or in the Board Trace Model window in the Pin Planner.

When Advanced I/O Timing is turned off, the TimeQuest analyzer computes delays with a linear model scaled with the data entered in the Capacitive Loading tab of the Device and Pin Options dialog box, or with the Output Pin Load logic option in the Pin Planner or Assignment Editor.

 

Scripting Information

Keyword:  enable_advanced_io_timing Settings: on | off

 

Note: Advanced I/O Timing is available only for supported device(Arria II GX, Arria V, Cyclone III, Cyclone IV, Cyclone V, Stratix III, Stratix IV, and Stratix V) families.

Directs the TimeQuest analyzer to perform multicorner timing analysis, which analyzes the design with the best-case (fast models) and worst-case (slow models) operating conditions.

 

Scripting Information

Keyword:  timequest_multicorner_analysis Settings:  on | off *default

 

Note: This feature is available only for supported device(Cyclone III, MAX II, Stratix III, and Stratix IV) families. This setting affects only TimeQuest analyzer reports that appear in the Compilation Report window. To change operating conditions in the TimeQuest analyzer graphical user interface, use the Set Operating Conditions dialog box.

Directs the TimeQuest analyzer to remove common clock path pessimism (CCPP) during slack computation.

 

Scripting Information

Keyword: timequest_do_ccpp_removal Settings:  on | off *default

Directs the TimeQuest analyzer to report the worst-case slack for each clock domain in the design.

 

Scripting Information

Keyword:  timequest_do_report_timing Settings:  on | off *default

Allows you to select a Tcl Script File that customizes reporting options.

 

Scripting Information

Keyword: timequest_report_script Settings:  <file name>

 

Turn on Run default timing analysis before running custom script to avoid missing any errors and warnings not triggered by your custom analysis.

 

Scripting Information

Keyword: timequest_report_script_include_default_analysis Settings:  on | off

 

Specifies the project-wide level of metastability analysis to perform during compilation. This option controls how aggressively the TimeQuest Timing Analyzer identifies registers as synchronization register chains for the entire design. A synchronization register chain is a sequence of registers with the same clock that is driven by a pin or logic from an unrelated clock domain. All but the last register in the chain must connect only to the next register.

You can override this project-wide setting with node or entity level assignments of the same name.

The available settings for project-wide synchronizer identification are:

• Off—The TimeQuest Timing Analyzer does not identify any registers in the design as synchronization registers.  

• Auto— the TimeQuest Timing Analyzer identifies valid synchronization registers that are part of a chain including more than one register that contains no combinational logic.

• Forced If Asynchronous— the TimeQuest Timing Analyzer identifies synchronization register chains if the software  detects an asynchronous signal transfer, even if there is combinational logic or only one register in the chain.

If a synchronization register chain meets the criteria of the selected option, the TimeQuest Timing Analyzer reports the Mean Time Between Failures (MTBF) for the chain.

By default, the first two registers of a synchronization chain are omitted from register retiming and duplication. You can specify other values by setting the Synchronization Register Chain Length in the More Analysis & Synthesis Settings dialog box.

This feature is available for supported device(Arria II GX, Arria V, Cyclone III, Cyclone IV, Cyclone V, Stratix III, Stratix IV, and Stratix V) families only.

 

Scripting Information

Keyword: synchronizer_identification Settings:  forced, forced_if_asynchronous, auto, off *default