Scripting

::quartus::sdc


The following table displays information for the ::quartus::sdc Tcl package:

Tcl Package and Version

::quartus::sdc 1.5

Description

Synopsys Design Constraint (SDC) format is used to specify the design
intent, including the timing and area constraints of the design.
The TimeQuest Timing Analyzer only implements the set of SDC commands
required to specify the timing constraints of the design. For area
constraints, the QSF file should be used.

This package implements the SDC Spec Version 1.5 (June 2005).

Any command in this package can be specified in a TimeQuest SDC
file.

Availability

This package is loaded by default in the following executable:

    quartus_sta

This package is available for loading in the following executable:

    quartus_fit

Tcl Commands

all_clocks
all_inputs
all_outputs
all_registers
create_clock
create_generated_clock
derive_clocks
get_cells
get_clocks
get_nets
get_pins
get_ports
remove_clock_groups
remove_clock_latency
remove_clock_uncertainty
remove_disable_timing
remove_input_delay
remove_output_delay
reset_design
set_clock_groups
set_clock_latency
set_clock_uncertainty
set_disable_timing
set_false_path
set_input_delay
set_input_transition
set_max_delay
set_min_delay
set_multicycle_path
set_output_delay