quad data rate (QDR) SRAM


QDR SRAM memory devices transfer data on separate read and write ports, and on both the rising edge and falling edge of the clock signal, resulting in four data throughputs per clock cycle. The dedicated input and output ports eliminate bus contention issues. Unilateral buses also simplify board design and facilitate high-frequency designs.

QDR SRAM devices use the HSTL I/O standard. QDR SRAMs are available for supported device families.


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