Advanced I/O Timing

About Advanced I/O Timing

 


The Advanced I/O Timing feature lets you describe a board trace and termination network as a set of capacitive, resistive, and inductive assignments. Advanced I/O Timing uses these assignments to simulate output signals to produce accurate output buffer-to-pin timing estimates, simple signal integrity analyses at the FPGA pin and at the far end of the board trace, and board trace delay values.

 

Note: Advanced I/O Timing is available only for these supported device families.

 

For Stratix II devices, you can turn on Advanced I/O Timing with the Enable Advanced I/O Timing checkbox in the Settings dialog box. For Arria II GX Arria II GZ, Cyclone III, Stratix III, Stratix IV, and Stratix V devices, Advanced I/O Timing is always enabled.

 

ExpandSimple I/O Timing Model:

ExpandAdvanced I/O Timing Model:

ExpandSignal Integrity Metrics report:

 

More information about Advanced I/O Timing is available on the Altera website.

 

 

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